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current output, parallel input, 16-/14-bit multiplying dacs with four-quadrant resistors data sheet ad5546 / ad5556 rev. d information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?2004-2011 analog devices, inc. all rights reserved. features 16-bit resolution 14-bit resolution 2- or 4-quadrant multiplying dac 1 lsb dnl 1 lsb inl operating supply voltage: 2.7 v to 5.5 v low noise: 12 nv/hz low power: i dd = 10 a 0.5 s settling time built-in r fb facilitates current-to-voltage conversion built-in 4-quadrant resistors allow 0 v to C10 v, 0 v to +10 v, or 10 v outputs 2 ma full-scale current 20%, with v ref = 10 v automotive operating temperature: C40c to +125c compact tssop-28 package applications automatic test equipment instrumentation digitally controlled calibration digital waveform generation functional block diagram dac ad5546/ ad5556 wr ldac msb rs db0 to db15 control logic dac register por 16/14 v dd r1 r2 r ofs r fb r1 r com ref r ofs r fb i out gnd 03810-001 figure 1. ad5546/ad5556 simplified block diagram general description the ad5546/ad5556 are precision 16-/14-bit, multiplying, low power, current output, parallel input digital-to-analog converters (dacs). they operate from a single 2.7 v to 5.5 v supply with 10 v multiplying references for four-quadrant outputs. built- in four-quadrant resistors facilitate the resistance matching and temperature tracking that minimize the number of components needed for multiquadrant applications. the feedback resistor (r fb ) simplifies the i-v conversion with an external buffer. the ad5546/ad5556 are packaged in compact tssop-28 packages with operating temperatures from C40c to +125c. the eval-ad5546sdz is available for evaluating dac perfor- mance. for more information, see the ug-309 evaluation board user guide. 03810-024 v dd r ofs r ofsa vout r fb r fba c6 gnd u1 ad5546/ad5556 i out r2 r1 r coma r1a 16-/14-bit data 16-/14-bit data vrefa u2b op2177 ? + c4 1f c5 0.1f c8 1f c9 0.1f +15v ?15v wr wr ldac ldac rs rs msb msb c2 0.1f c1 1f v+ v? u2a op2177 + ? c7 +5v +10v ? 10v figure 2. 16-/14-bit, four-quadrant multiplying dac with a minimum of external components
ad5546/ad5556 data sheet rev. d | page 2 of 20 table of contents features .............................................................................................. 1 applications ....................................................................................... 1 functional block diagram .............................................................. 1 general description ......................................................................... 1 revision history ............................................................................... 2 specifications ..................................................................................... 3 electrical characteristics ............................................................. 3 timing diagram ........................................................................... 4 absolute maximum ratings ............................................................ 5 esd caution .................................................................................. 5 pin configurations and function descriptions ........................... 6 typical performance characteristics ............................................. 8 circuit operation ........................................................................... 10 digital - to - analog (dac) converter section ......................... 10 digital section ............................................................................ 11 esd protec tion circuits ............................................................ 11 amplifier selection .................................................................... 11 reference selection .................................................................... 11 a pplications information .............................................................. 12 unipolar mode ........................................................................... 12 bipolar mode .............................................................................. 13 ac r eference signal attenuator ............................................... 14 system calibration ..................................................................... 14 reference selection .................................................................... 15 amplifier selection .................................................................... 15 outline dimensions ....................................................................... 17 ordering guide .......................................................................... 17 r evision h istory 11/11 rev. c to rev. d changes to general description section ...................................... 1 changes to ordering guide .......................................................... 18 1/ 11 rev. b to rev. c changes to figure 2 .......................................................................... 1 changes to figure 21 ...................................................................... 13 4/10 re v. a to rev. b changes to table 1 ............................................................................ 4 moved timing diagram section and figure 5 to specif ications section ....................................................................... 4 moved table 5 through table 7 to digital section section ....... 7 replaced figure 15 and figure 16 .................................................. 9 deleted figure 17 and figure 18 ..................................................... 9 added reference selection section, amplifier selection section, and table 11 through table 13 .................................................... 15 9 /09 rev. 0 to rev. a changes to features section ............................................................ 1 changes to static performance, relative accuracy, grade: ad5546c parameter, table 1 ............................................. 3 changes to ordering guide .......................................................... 16 1/04 revision 0: initial version
data sheet ad5546/ad5556 rev. d | page 3 of 20 specifications electrical character istics v dd = 2.7 v to 5.5 v, i out = virtual gnd, gnd = 0 v, v ref = C 10 v to 10 v, t a = full operating temperature range, unless otherwise noted. table 1 . parameter symbol conditions min typ max unit static performance 1 resolution n ad5546, 1 lsb = v ref /2 16 = 153 v at v ref = 10 v 16 bits ad5556, 1 lsb = v ref /2 14 = 610 v at v ref = 10 v 14 bits relative accuracy inl grade: ad5556c 1 lsb grade: ad5546b 2 lsb grade: ad5546c 1 lsb differential nonlinearity dnl monotonic 1 lsb o utput leakage current i out data = zero scale, t a = 25c 10 na data = zero scale, t a = t a maximum 20 na full - scale gain error g fse data = full scale 1 4 mv bipolar mode gain error g e data = full scale 1 4 mv bipolar mode zero - scale error g zs e data = full scale 1 2.5 mv full - scale tempco 2 tcv fs 1 ppm/c reference input v ref range v ref C 18 +18 v ref input resistance ref 4 5 6 k? r1 and r2 resistance r1 and r2 4 5 6 k? r1 -to - r2 mismatch ?( r1 to r2) 0.5 1.5 ? feedback and offset resistance r fb , r ofs 8 10 12 k? input capacitance 2 c ref 5 pf analog output output current i out data = full scale 2 ma output capac itance 2 c out code dependent 200 pf logic input and output logic input low voltage v il v dd = 5 v 0.8 v v dd = 3 v 0.4 v logic input high voltage v ih v dd = 5 v 2.4 v v dd = 3 v 2.1 v input leakage curr ent i il 10 a input capacitance 2 c il 10 pf interface timing 2 , 3 data to wr setup time t ds v dd = 5 v 20 ns v dd = 3 v 35 ns data to wr hold time t dh v dd = 5 v 0 ns v dd = 3 v 0 ns wr pulse width t wr v dd = 5 v 20 ns v dd = 3 v 35 ns ldac pulse width t ldac v dd = 5 v 20 ns v dd = 3 v 35 ns
ad5546/ad5556 data sheet rev. d | page 4 of 20 parameter symbol conditions min typ max unit rs pulse width t rs v dd = 5 v 20 ns v dd = 3 v 35 ns wr to ldac delay time t lwd v dd = 5 v 0 ns v dd = 3 v 0 ns supply characteristics power supply range v dd range 2.7 5.5 v positive supply current i dd logic inputs = 0 v 10 a power dissipation p diss logic inputs = 0 v 0.055 mw power supply sensitivity p ss ?v dd = 5% 0.003 %/% ac characteristics 4 output voltage settling time t s to 0.1% of full scale, data cycles from zero scale to full scale to zero scale 0.5 s reference multiplying bw bw v ref = 100 mv rms, data = full scale, c6 =5.6 pf 5 6.8 mhz dac glitch impulse q v ref = 0 v, midscale minus 1 to midscale ?3 nv-s multiplying feedthrough error v out /v ref v ref = 100 mv rms, f = 10 khz 79 db digital feedthrough q d wr = 1, ldac toggles at 1 mhz 7 nv-s total harmonic distortion thd v ref = 5 v p-p, data = full-scale, f = 1 khz C103 db output noise density e n f = 1 khz, bw = 1 hz 12 nv/rt hz 1 all static performance tests (except i out ) are performed in a closed-loop system, using an external precision op97 i-v conver ter amplifier. the ad554x rfb terminal is tied to the amplifier output. the op amp +in is grounded, and the dac i out is tied to the op amp Cin. typical values represent average readin gs measured at 25c. 2 these parameters are guaranteed by design and are not subject to production testing. 3 all input control signals are specified with t r = t f = 2.5 ns (10% to 90% of 3 v) and timed from a voltage level of 1.5 v. 4 all ac characteristic tests are performe d in a closed-loop system us ing an ad8038 i-v converter ampli fier except for thd where an ad8065 was used. 5 c6 is the c6 capacitor shown in figure 20. timing diagram 03810-005 t wr t ds t dh t lwd t ldac t rs wr data ldac rs figure 3. ad5546/ad5556 timing diagram
data sheet ad5546/ad5556 rev. d | page 5 of 20 absolute maximum rat ings table 2 . parameter rating v dd to gnd C 0.3 v, +8 v r fb , r ofs , r 1 , r com , and ref to gnd C 18 v, 18 v logic inputs to gnd C 0.3 v, +8 v v (i out ) to gnd C 0.3 v, v dd + 0.3 v input current to an y pin e xcept supplies 50 ma thermal resistance ( ja ) 128c maximum junction temperature (t j max ) 150c operating temperature range C 40c to +125c storage temperature range C 65c to +150c lead temperature: vapor phase, 60 s 215c in frared, 15 s 220c package power dissipation (t j max C t a )/ ja stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other co nditions above those listed in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. esd caution
ad5546/ad5556 data sheet rev. d | page 6 of 20 p in configurations and function de scriptions 03810-003 ad5546 top view (not to scale) d7 1 v dd 28 d6 2 d8 27 d5 3 d9 26 d4 4 d10 25 d3 5 d11 24 d2 6 d12 23 d1 7 d13 22 d0 8 d14 21 r ofs 9 d15 20 r fb 10 gnd 19 r1 11 rs 18 r com 12 msb 17 ref 13 wr 16 i out 14 ldac 15 figure 4. ad5546 pin configuration 03810-004 ad5556 top view (not to scale) nc = no connect d5 1 v dd 28 d4 2 d6 27 d3 3 d7 26 d2 4 d8 25 d1 5 d9 24 d0 6 d10 23 nc 7 d11 22 nc 8 d12 21 r ofs 9 d13 20 r fb 10 gnd 19 r1 11 rs 18 r com 12 msb 17 ref 13 wr 16 i out 14 ldac 15 figure 5 . ad5556 pin configuration table 3 . ad5546 pin function descriptions pin no. mnemonic description 1 to 8 d7 to d0 di gital input data bits [ d7 : d0 ] . the s ignal level must be v dd + 0.3 v. 9 r ofs bipolar offset resistor. accepts up to 18 v. in two - quadrant mode , ties to r fb . in four - quadrant mode , ties to r1 and the external reference. 10 r fb internal matching feedback resistor. connects to the output of an external op amp for i - v conversion. 11 r1 four - qua drant resistor r1. in two - quadrant mode , shorts to the ref pin. in four - quadrant mode , ties to r ofs . 12 r com center tap point of two four - quadrant resistors, r1 and r2. in four - quadrant mode, ties to the inverting node of the reference amplifier. in two - quadrant mode, shorts to the ref pin. 13 ref dac reference input in two - quadrant mode and r2 terminal in four - quadrant mode. in two - quadrant mode, this pin is the re ference input with constant input resistance vs. code. in four - quadrant mode, this pin is driven by the external reference amplifier. 14 i out dac current output. connects to the inverting node of an external op amp for i - v conversion. 15 ldac digital inp ut load dac control. signal level must be v dd + 0.3 v. 16 wr write control digital input in active low. transfers shift - register data to the dac register on the rising edge. the s ignal level must be v dd + 0.3 v. 17 msb power - on reset state. msb = 0 resets at zero scale; msb = 1 resets at midscale. the s ignal level must be v dd + 0.3 v. 18 rs reset in active low. resets to zero scale if msb = 0, and resets to midscale if msb = 1. the s ignal level must be v dd + 0.3 v. 19 gnd analog and digital grounds. 20 to 21 d15 to d14 digital input data bits[d15: d14 ] . the s ignal level must be v dd + 0.3 v. 22 to 27 d13 to d8 digital input data bits [ d13 : d8 ] . the s ignal level must be v dd + 0.3 v. 28 v dd positive power supply input. specified range of operation: 2.7 v to 5.5 v. table 4 . ad5556 pin function descriptions pin no. mnemonic description 1 to 6 d5 to d0 digital input data bits [d5: d0 ] . the s ignal level must be v dd +0.3 v. 7 to 8 nc no connection. the u ser should not connect any thing other than dummy pads on these terminals. 9 r ofs bipolar offset resistor. accepts up to 18 v. in two - quadrant mode , ties to rfb. in four - quadrant mode , ties to r1 and the external reference. 10 r fb internal matching feedback resistor. connects to the output of an external op amp for i - v conversion. 11 r1 four - qua drant resistor r1. in two - quadrant mode , shorts to the ref pin. in four - quadrant mode , ties to r ofs . 12 r com center tap point of two four - quadrant resistors, r1 and r2. in four - quadrant m ode, ties to the inverting node of the reference amplifier. in two - quadrant mode, shorts to the ref pin.
data sheet ad5546/ad5556 rev. d | page 7 of 20 pin no. mnemonic description 13 ref dac reference input in two - quadrant mode and r2 terminal in four - quadrant mode. in two - quadrant mode, this pin is the reference input with cons ta nt input resistance vs. code. in four - quadrant mode, this pin is driven by the external reference amplifier. 14 i out dac current output. connects to the inverting node of an external op amp for i - v conversion. 15 ldac digital input load dac control. th e signal level must be v dd + 0.3 v. 16 wr write control digital input in active low. transfers shift - register data to the dac register on the rising edge. the s ignal level must be v dd + 0.3 v. 17 msb power on reset state. msb = 0 r es ets at zero scal e; msb = 1 resets at midscale. the si gnal level must be v dd + 0.3 v. 18 rs rese t in active low. resets to zero scale if msb = 0 and resets to midscale if msb = 1. the s ignal level must be v dd + 0.3 v. 19 gnd anal og and digital grounds. 20 to 27 d13 to d6 digital input data bits [ d13 : d6 ] . the s ignal level must be v dd + 0.3 v. 28 v dd positive p ower s upply i nput. specified range of operation: 2.7 v to 5.5 v.
ad5546/ad5556 data sheet rev. d | page 8 of 20 typical performance characteristics 03810-006 1.0 0.8 0.6 0 8192 16,384 24,576 32,768 40,960 49,152 57,344 65,536 0.4 0.2 0 ?0.2 ?0.4 ?0.6 ?0.8 ?1.0 inl (lsb) code (decimal) figure 6. ad5546 integral nonlinearity error 03810-007 1.0 0.8 0.6 0 8192 16,384 24,576 32,768 40,960 49,152 57,344 65,536 0.4 0.2 0 ?0.2 ?0.4 ?0.6 ?0.8 ?1.0 dnl (lsb) code (decimal) figure 7. ad5546 differential nonlinearity error 03810-008 1.0 0.8 0.6 0 2048 4096 6144 8192 10,240 12,288 14,336 16,384 0.4 0.2 0 ?0.2 ?0.4 ?0.6 ?0.8 ?1.0 inl (lsb) code (decimal) figure 8. ad5556 integral nonlinearity error 03810-009 1.0 0.8 0.6 0 0248 4096 6144 8192 10,240 12,288 14,336 16,384 0.4 0.2 0 ?0.2 ?0.4 ?0.6 ?0.8 ?1.0 dnl (lsb) code (decimal) figure 9. ad5556 differential nonlinearity error 03810-010 1.5 1.0 24 ge dnl inl 6810 0.5 0 ?0.5 ?1.0 ?1.5 linearity error (lsb) supply voltage v dd (v) v ref = 2.5v t a = 25c figure 10. linearity error vs. v dd 03810-011 5 4 0 0.5 1.0 1.5 2.0 3.0 3.5 2.5 4.0 4.5 5.0 3 2 1 0 supply current i dd (lsb) logic input voltage v ih (v) v dd = 5v t a = 25c figure 11. supply current vs. logic input voltage
data sheet ad5546/ad5556 rev. d | page 9 of 20 03810-012 3.0 2.5 10k 100k 1m 10m 100m 2.0 1.5 1.0 0.5 0 supply current (ma) clock frequenc y (hz) 0x5555 0x8000 0xffff 0x0000 figure 12 . ad5546 supply current vs. clock frequency 03810-013 90 70 10 100 1k 10k 100k 1m 50 40 60 80 30 10 20 0 psrr (?db) frequenc y (hz) v dd = 5 v 10% v ref = 10v figure 13 . power supply rejection ratio vs. frequency 03810-014 ldac v out 1 2 ch1 5.00v ch2 2.00v m 200ns a ch1 2.70v b ch1 ?6.20v 400.00ns figure 14 . settling time from full scale to zero scale ?4.20 ?4.15 ?4.10 ?4.05 ?4.00 ?3.95 ?3.90 ?3.85 ?3.80 ?200 ?100 0 100 200 300 400 time (ns) v out (v) 03810- 1 15 figure 15 . ad5546 midscale transition ?18 ?16 ?14 ?12 ?10 ?8 ?6 ?4 ?2 0 2 10k 100k 1m 10m 100m frequenc y (hz) gain (db) 03810- 1 16 figure 16 . ad5546 unipolar reference multiplying bandwidth
ad5546/ad5556 data sheet rev. d | page 10 of 20 circuit operation digital-to-analog (dac) converter section the ad5546/ad5556 are 16-/14-bit multiplying, current out- put, and parallel input dacs. the devices operate from a single 2.7 v to 5.5 v supply and provide both unipolar 0 v to Cv ref , or 0 v to +v ref , and bipolar v ref output ranges from a C18 v to +18 v reference. in addition to the precision conversion r fb commonly found in current output dacs, there are three addi- tional precision resistors for four-quadrant bipolar applications. the ad5546/ad5556 consist of two groups of precision r-2r ladders, which make up the 12/10 lsbs, respectively. further- more, the four msbs are decoded into 15 segments of resistor value 2r. figure 17 shows the architecture of the 16-bit ad5546. each of the 16 segments in the r-2r ladder carries an equally weighted current of one-sixteenth of full scale. the feedback resistor, r fb , and four-quadrant resistor, r ofs , have values of 10 k. each four-quadrant resistor, r1 and r2, equals 5 k. in four-quadrant operation, r1, r2, and an external op amp work together to invert the reference voltage and apply it to the ref input. with r ofs and r fb connected as shown in figure 2, the output can swing from Cv ref to +v ref . the reference voltage inputs exhibit a constant input resistance of 5 k 20%. the dac output, i out , impedance is code depen- dent. external amplifier choice should take into account the variation of the ad5546/ad5556 output impedance. the feedback resistance in parallel with the dac ladder resistance dominates output voltage noise. to maintain good analog performance, it is recommended to bypass the power supply with a 0.01 f to 0.1 f ceramic or chip capacitor in parallel with a 1 f tantalum capacitor. also, to minimize gain error, pcb metal traces between v ref and r fb should match. every code change of the dac corresponds to a step function; gain peaking at each output step may occur if the op amp has limited gbp and excessive parasitic capacitance present at the op amp inverting node. a compensation capacitor, therefore, may be needed between the i-v op amp inverting and output nodes to smooth the step transition. such a compensation capacitor should be found empirically, but a 20 pf capacitor is generally adequate for the compensation. the v dd power is used primarily by the internal logic and to drive the dac switches. note that the output precision degrades if the operating voltage falls below the specified voltage. the user should also avoid using switching regulators because device power supply rejection degrades at higher frequencies. 03810-019 2r 80k? r 40k? 2r 80k? 2r 80k? 2r 80k? 2r 80k ? 2r 80k ? r 40k ? 2r 80k ? r 2r 80k ? r 2r 80k ? r 2r 80k? r 2r 80k? 2r 80k ? r 40k ? r2 5k? r1 5k? ref 2r 80k ? r 40k ? 2r 80k? r 40k ? 2r 80k? r 40k ? 2r 80k? r 40k? 2r 80k? r 40k? 2r 80k ? r com r1 address decoder dac register input register ldac wr rs rs 4 msb 15 segments 8-bit r?2r 4-bit r?2r 16 8 4 ldac wr d15 d14 d0 rs 10k? 10k ? r ofs r fb i out gnd ra rb figure 17. 16-bit ad5546 equivalent r-2r dac circuit with digital section
data sheet ad5546/ad5556 rev. d | page 11 of 20 digital section the ad5546/ad5556 have 16 - /14 - bit parallel inputs. the devices are double buffered with 16 - /14 - bit registers. the double - buffered feature allow s the update of several ad5546/ad5556 simultaneously. for the ad5546, the input register is loa ded directly from a 16 - bit controller bus when the wr pin is brought low. the dac register is updated with data from the input register when ldac is brought high. updating the dac register updates the dac output with the new data (see figure 17 ). to make both registers transparent, tie wr low and ldac high. the asynchronous rs pin resets the part to zero scale if the msb pin = 0 and to midscale if the msb pin = 1. table 5 . ad5546 parallel input data format msb lsb bit position b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 data word d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 table 6 . ad5556 paralle l input data format msb lsb bit position b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 data word d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 table 7 . control inputs rs wr ldac re gister operation 0 x 1 x 1 reset output to 0, with msb pin = 0 and to midscale with msb pin = 1. 1 0 0 load input register with data bits. 1 1 1 load dac register with the contents of the input register. 1 0 1 input and d ac registers are transparent. 1 when ldac and wr are tied together and programmed as a pulse, the data bits are loaded into the input register on the falling edge of the pulse and then loaded into the dac register on the rising edge of the pulse. 1 1 0 no register operation. 1 x = dont care. esd protection circu its all logic input pins contain back - biased esd protection zeners connected to ground (gnd) and v dd , as shown in figure 18 . as a result, the voltage level of the l ogic input should not be greater than the supply voltage. 03810-020 5k? digi tal inputs dgnd v dd figure 18 . equivalent esd protection circuits amplifier selection in addition to offset voltage, the bias current is important in op amp selection for precision current ou tput dacs. an input bias current of 30 na in the op amp contributes to 1 lsb in the ad5546s full - scale error. the op1177 and ad8628 op amps are good candidates for the i - v conversion. reference selection the initial accuracy and the rated output of the vo ltage refer - ence determine the full span adjustment. the initial accuracy is usually a secondary concern in precision because it can be trimmed. figure 23 shows an example of a trimming circuit. the zero scale error can also be minimized by standard op amp nulling techniques. the voltage reference temperature coefficient (tc) and long - term drift are primary considerations. for example, a 5 v ref - erence with a tc of 5 ppm/ o c means that the output changes by 25 v per degree celsius. as a result, the reference that operates at 55 o c contributes an additional 750 v full - scale error. similarly, the same 5 v reference with a 50 ppm long - term drift means that the output may change by 250 v over time. therefore, it is practical to ca librate a system periodically to maintain its optimum precision.
ad5546/ad5556 data sheet rev. d | page 12 of 20 applications information unipolar mode two - quadrant multiplying mode, v out = 0 v to Cv ref the ad5546/ad5556 dac architecture uses a current - steering r- 2r ladder design that requires an e xternal reference and op amp to convert the unipolar mode of output voltage to ad5546 v out = C v ref d /65,536 (1) ad5556 v out = C v ref d /1 6,384 (2) where d is the decimal equivalent of the input code. the output voltage polarity is opposite to the v ref p olarity in this case (see figure 19 ). table 8 shows the negative output vs. code for the ad5546. table 8 . ad5546 unipolar mode negative output vs. code d in binary v out (v) 1111 1111 1111 1111 Cv ref (65,535/65,536) 1000 0000 0000 0000 Cv ref /2 0000 0000 0000 0001 Cv ref (1/65,536) 0000 0000 0000 0000 0 two - quadrant multiplying mode, v out = 0 v to +v ref the ad5546/ad5556 are designed to operate with either positive or negative refere nce voltages. as a result, positive output can be achieved with an additional op amp, (see figure 20 ), and the output becomes ad5546 v out = +v ref d /65,536 (3) ad5556 v out = +v ref d /16,384 (4) table 9 s hows the positive output vs. code for the ad5546. table 9 . ad5546 unipolar mode positive output vs. code d in binary v out (v) 1111 1111 1111 1111 +v ref (65,535/65,536) 1000 0000 0000 0000 +v ref /2 0000 0000 0000 0001 +v ref (1/65,536 ) 0000 0000 0000 0000 0 03810-021 2 +5v 5 4 g nd v in trim u3 adr03 v out v dd r1 r ofs r ofs vout ?2.5v t o 0v r fb r fb c6 2.2pf gnd u1 ad5546/ad5556 i out r2 c4 0.1f c5 1f r com r1 16-/14-bit dat a 16-/14-bit dat a ref u2 ad8628 ? + ?5v wr wr ldac ldac rs rs msb msb c2 0.1f c1 1f c3 0.1f v+ v? figure 19 . unipolar two - quadrant multiplying mode, v out = 0 to ?v ref
data sheet ad5546/ad5556 rev. d | page 13 of 20 03810-024 v dd r ofs r ofs a vout r fb r fb a c6 gnd u1 ad5546/ad5556 i out r2 r1 r com a r1 a 16-/14-bit dat a 16-/14-bit d at a vre fa u2b op2177 ? + c4 1f c5 0.1f c8 1f c9 0.1f +15v ?15v wr wr ldac ldac rs rs msb msb c2 0.1f c1 1f v+ v? u2 a op2177 + ? c7 +5v +10v ?10v figure 20 . unipolar two - quadrant multiplying mode, v out = 0 to +v ref 2 5v 6 5 4 gnd v in trim u3 adr03 v out 5v v dd r1 r ofs r ofs ?vref t o +vref vout r fb r fb c2 gnd u1 ad5546/ad5556 i out r2 u2 a op2177 + ? c1 ?vref +vref r com r1 16-/14-bit dat a 16-/14-bit dat a ref u2b op2177 ? + wr wr ldac ldac rs rs msb msb 03810-002 figure 21 . four - quadrant multiplying mode, v out = Cv ref to +v ref bipolar mode four - quadrant multiplying mode, v out = Cv ref to +v ref the ad5546/ad5556 contain on - chip all the four - quadrant resistors necessary for the precision bipolar multiplying operation. such a feature minimizes the number of exponent components to only a voltage reference, dual op amp, and compensation capacitor (see figure 21 ). for example, with a 10 v reference, the circuit yields a precision, bipolar C 10 v to +10 v output. ad5546 v out = ( d /32768 ? 1) v ref (5) ad5556 v out = ( d /16384 ? 1) v ref (6) table 10 shows some of the results for the 16 - bit ad5546.
ad5546/ad5556 data sheet rev. d | page 14 of 20 table 10. ad5546 output vs. code d in binary v out 1111 1111 1111 1111 +v ref (32,767/32,768) 1000 0000 0000 0001 +v ref (1/32,768) 1000 0000 0000 0000 0 0111 1111 1111 1111 Cv ref (1/32,768) 0000 0000 0000 0000 Cv ref ac reference signal attenuator besides handling digital waveforms decoded from parallel input data, the ad5546/ad5556 handle equally well low frequency ac reference signals for signal attenuation, channel equalization, and waveform generation applications. the maximum signal range can be up to 18 v (see figure 22). system calibration the initial accuracy of the system can be adjusted by trimming the voltage reference adr0x with a digital potentiometer (see figure 23). the ad5170 provides an otp (one time program- mable), 8-bit adjustment that is ideal and reliable for such cali- bration. the analog devices, inc., otp digital potentiometer comes with programmable software that simplifies the factory calibration process. 03810-0-024 16/14-bit vdd rofs rofsa vout rfb rfba c6 gnd u1 ad5546/ad5556 iout r2 r1 rcoma r1a 16/14 data vrefa u2b op2177 ? + c4 1 ? f c5 0.1? f c8 1 ? f c9 0.1? f +15v ?15v wr wr ldac ldac rs rs msb msb c2 0.1? f c1 1 ? f v+ v? u2a op2177 + ? c7 +5v +10v ?10v figure 22. signal attenuator with ac reference c8 0.1f c9 1f ?5v 03810-025 16-/14-bit data 16-/14-bit data 2 +5v 5 6 4 gnd v in trim u3 adr03 v out v dd r ofs r3 470k ? u4 ad5170 10k ? b r7 1k ? r ofsa vout 0v to +2.5v r fb r fba c6 gnd u1 ad5546/ad5556 i out r2 r1 r coma r1a +2.5v vrefa u2b ad8628 ? + c4 1f c5 0.1f +5v wr wr ldac ldac rs rs msb msb c2 0.1f c1 1f c3 0.1f v+ v? u2a ad8628 + ? c7 ?2.5v v+ v? figure 23. full span calibration
data sheet ad5546/ad5556 rev. d | page 15 of 20 reference selection when selecting a reference for use with the ad55xx series of current output dacs, pay attention to the output voltage temperature coefficient specification of the reference. c hoosing a precision reference with a low ou tput temperature coefficient minimize s error sources . table 11 lists some of the references available from analog devices that are suitable for use with this range of current output dacs. amplifier selection the primary requirement for the current - steering mode is an amplifier with low input bias currents and low input offset voltage. because of the code - dependent output resistance of the dac , th e input offset voltage of an op amp is multiplied by the variable gain of the circuit. a change in this noise gain between two adjacent digital fractions produces a step change in the output voltage due to the amplifiers input offset voltage. this output v oltage change is superimposed on the desired change in output between the two codes and gives rise to a differential linearity error, which, if large enough, can cause the dac to be nonmonotonic. the input bias cu r rent of an op amp also generates an offset at the voltage output because of the bias current flowing in the feedback resistor , r fb . common - mode rejection of the op amp is important in voltage - switching circuits because it produces a code - dependent error at the voltage output of the circuit. provided that the dac switches are driven from true wideband low impedance sources, they set tle quickly. consequently, the slew rate and settling time of a voltage - switching dac circuit is determined largely by the output op amp. to obtain minimum settling time in this configuration, minimize capacitance at the v ref node ( the voltage output node in this application) of the dac. this is done by usin g low input capacitance buffer amplifiers and careful board design. analog devices offers a wide range of amplifiers for both precision dc and ac applications , as listed in table 12 and table 13. table 11. suitable analog devices precision references part no. output voltage (v) initial tolerance (%) maximum temp erature drift (ppm/c) i ss (ma) output noise (v p - p) package (s) adr01 10 0.05 3 1 20 soic-8 adr01 10 0.05 9 1 20 tsot - 5, sc70 -5 adr02 5 .0 0.06 3 1 10 soic-8 adr02 5 .0 0.06 9 1 10 tsot - 5, sc70 -5 adr03 2.5 0.1 3 1 6 soic-8 adr03 2.5 0.1 9 1 6 tsot - 5, sc70 -5 adr06 3 .0 0.1 3 1 10 soic-8 adr06 3 .0 0.1 9 1 10 tsot - 5, sc70 -5 ADR420 2.048 0.05 3 0.5 1.75 soic- 8, msop -8 adr421 2.50 0.04 3 0.5 1.75 soic- 8, msop -8 adr423 3.00 0.04 3 0.5 2 soic- 8, msop -8 adr425 5.00 0.04 3 0.5 3.4 soic- 8, msop -8 adr431 2.500 0.04 3 0.8 3.5 soic- 8, msop -8 adr435 5 .000 0.04 3 0.8 8 soic- 8, msop -8 adr391 2.5 0.16 9 0.12 5 tsot -5 adr395 5 .0 0.10 9 0.12 8 tsot -5
ad5546/ad5556 data sheet rev. d | page 16 of 20 table 12 . suitable analog devices precision op amps part no. supply voltage (v) v os max imum (v) i b max imum (na) 0.1 hz to 10 hz noise (v p - p) supply current (a) package (s) op97 2 to 20 25 0.1 0.5 600 soic- 8 , pdip -8 op1177 2.5 to 15 60 2 0.4 500 msop - 8, soic -8 ad8675 5 to 18 75 2 0.1 2300 ms op - 8, soic -8 ad8671 5 to 15 75 12 0.077 3000 msop - 8, soic -8 ada4004 -1 5 to 15 125 90 0.1 2000 soic-8 , sot -23 -5 ad8603 1.8 to 5 50 0.001 2.3 40 tsot -5 ad8607 1.8 to 5 50 0.001 2.3 40 msop - 8, soic -8 ad8605 2.7 to 5 65 0.001 2.3 1000 wlcsp - 5, sot -23 -5 ad8615 2.7 to 5 65 0.001 2.4 2000 tsot -23- 5 ad8616 2.7 to 5 65 0.001 2.4 2000 msop - 8, soic -8 table 13. suitable analog devices high speed op amps part no. supp ly voltage (v) bw @ acl (mhz) slew rate (v/s) v os (max) (v) i b (max) (na) package (s) ad8065 5 to 24 145 180 1500 0.006 soic- 8, sot -23-5 ad8066 5 to 24 145 180 1500 0.006 soic- 8, msop -8 ad8021 5 to 24 490 1 20 1000 10,500 soic- 8, msop -8 ad8038 3 to 12 350 425 3000 750 soic- 8, sc70 -5 ada4899 -1 5 t o 12 600 310 35 100 lfcsp - 8, soic -8 ad8057 3 to 12 325 1000 5000 500 sot -23- 5, soic -8 ad8058 3 to 12 325 850 5000 500 soic- 8, msop -8 ad8061 2.7 to 8 320 650 6 000 350 sot -23- 5, soic-8 ad8062 2.7 to 8 320 650 6000 350 soic- 8, msop -8 ad 9631 3 to 6 320 1300 10, 000 7000 soic-8 , pdip -8
data sheet ad5546/ad5556 rev. d | page 17 of 20 outline dimensions compliant to jedec standards mo-153-ae 28 15 14 1 8 0 seating plane coplanarity 0.10 1.20 max 6.40 bsc 0.65 bsc pin 1 0.30 0.19 0.20 0.09 4.50 4.40 4.30 0.75 0.60 0.45 9.80 9.70 9.60 0.15 0.05 figure 24 . 28 - lead thin shrink small outline package [tssop] ru - 28 dimensions shown in millimeters ordering guide model 1 res (bit) dnl (lsb) inl (lsb) temperature range ( c) package description package option ordering quantity ad5546bru 16 1 2 ?40 to +125 28- lead tssop ru -28 50 ad5546bru - reel7 16 1 2 ?40 to +125 28- lead tssop ru -28 1, 000 ad5546bruz 16 1 2 ?40 to +125 28- lead tssop ru -28 50 ad5546bruz - reel7 16 1 2 ?40 to +125 28- lead tssop ru -28 1, 000 ad5546cruz 16 1 1 ?40 to +125 28- lead tssop ru -28 50 ad5546cruz - reel7 16 1 1 ?40 to +125 28- lead tssop ru -28 1, 000 ad5556cru 14 1 1 ?40 to +125 28- lead tssop ru -28 50 ad5556cru - reel 7 14 1 1 ?40 to +125 28- lead tssop ru -28 1, 000 ad5556cruz 14 1 1 ?40 to +125 28- lead tssop ru -28 50 eval - ad5546sdz evaluation board 1 z = rohs compliant part.
ad5546/ad5556 data sheet rev. d | page 18 of 20 notes
data sheet ad5546/ad5556 rev. d | page 19 of 20 notes
ad5546/ad5556 data sheet rev. d | page 20 of 20 notes ? 2004 - 2011 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d03810 -0- 11/11(d)

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